A burst mode is known to be used in some memory devices to increase the speed of reading and writing data from and to the memory. Burst mode operation allows reads or writes from or to consecutive memory core locations at high speeds. When a burst mode is not implemented, a memory storage device uses one clock cycle to activate a row, giving the row address, and another clock cycle for column addressing. The READ or WRITE command is given with the column address on separate command lines.
In the clock cycle(s) following the addressing/command cycles, data is transferred from or to a memory device. For example, 4 eight bit data bytes being read from or written to a DDR SDRAM requires one clock cycle to decode each of the four column addresses. The first column address is issued with the READ or WRITE command with the subsequent column address being decoded internally on the DRAM device freeing up the command bus for other uses.
In addition, by eliminating column decoding time, the command bus is free to reduce latency during back intervening. Accordingly, a burst mode operation provides relatively high data transfer rates and significantly reduces the latency involved in a memory transfer.
The burst mode is generally controlled by setting one or more bits in a mode register provided within a memory device. As shown in FIG. 1, which depicts one exemplary memory device mode register, data within the mode register 100 controls a variety of different chip functions. Bits 13 and 14 of mode register 100 are used to select between a base mode register and an extended mode register; bits 7 through 12 of mode register 100 determine the operating mode of the memory device; bits 4-6 of mode register 100 determine the column address strobe (“CAS”) latency; bit 3 of mode register 100 determines whether the burst type is sequential or interleaved; and, bits 0-2 of mode register 100 determine the burst length.
The burst length determines the maximum number of consecutive column locations that can be accessed for a given READ or WRITE command without the need to use clock cycles to transfer subsequent intervening column addresses. As shown in tables 110 and 120, burst lengths of 2, 4 or 8 bytes can be selected for each of the sequential and interleaved burst types which is set by bit position 3.
Mode register 100 is programmed by a CPU or memory controller using a MODE REGISTER SET command and retains the set information until it is programmed again, or the memory device loses power. The mode register must be programmed while all memory cores are idle and no data bursts are in progress, and the memory controller or CPU must wait a specified time before initiating a memory access operation subsequent to programming.
A memory device which allows dynamic programming of burst length would be desirable and would permit faster adjustment of the burst length.